Power MOSFETs have typically been developed for applications requiring power switching and power amplification. For power switching applications, the commercially available devices are typically double diffused MOSFETs (DMOSFETs). Although a semiconductor power device with a planar gate structure is more compatible with multiple foundries and can be produced at a lower production cost, conventional technologies for manufacturing a MOSFET device with planar gates are still challenged by several technical difficulties and limitations. Referring to FIG. 1A, which is a cross-sectional view for a single cell 100 of a typical conventional vertical DMOS field effect transistor (FET) device configured with a planar structure having horizontal channel and gate, the channel is diffused from the edge of the source region near the gate. A DMOS FET typically includes a large number of such cells. The vertical FET structure of the cell 100 is formed on an N+ substrate 102, which acts as a drain region. An N-Epitaxial (epi) or N-drift 104 is located on top of the substrate 102. The structure 100 also includes a P-body region 106, an N+ source region 108, a N+ polysilicon gate region 112 and a gate oxide 110 disposed under the N+ gate 112. The transistor cell 100 in the example shown in FIG. 1A is an n-channel MOSFET (NMOSFET). A JFET implant, e.g., a N-type dopant implant for a NMOSFET device, may be used to reduce an increase of the on-resistance Rdson caused by the lateral pinching by the body regions 106 of the drift region 104 between the channel regions 106. However, such a device has limited high frequency applications at a low bias due to the high gate-to-drain capacitance caused by the coupling of the planar gates to drain across the epitaxial and drift regions between the body regions. A JFET implant may be used to reduce the Rdson will increase the gate-drain capacitance.
Furthermore, a DMOS device with planar gate is limited by several technical limitations that the cell pitch cannot be easily reduced. Specifically, in reducing a cell pitch of a DMOS device, a small distance between the body regions causes a high drain to source on-resistance Rds-on. Baliga disclosed in U.S. Pat. No. 6,800,897 and U.S. Pat. No. 6,791,143 a SSCFET (Silicon Semiconductor Corporation FET) device as shown in FIG. 1B, which illustrates a cross-sectional view of a SSCFET cell structure 120. For an n-channel MOSFET device, the SSCFET cell structure 120 is implemented with a deep retrograde N-type implant region 114 to improve device on resistance. The JFET implant region 114 is further combined with a buried P-region 116 disposed beneath the P-body region 106 to shield a shallow “conventional” laterally diffused channel. However, the SSCFET structure as shown in FIG. 1B does not provide an effective resolution to the above-described technical difficulties due to competing design requirements. Specifically, a high dose JFET implant for the purpose of achieving a lower resistance also compensates the P-body and the P-shield implant regions. It is also difficult to optimize and manufacture the SSCFET cell structure. For these reasons, demands for a high performance power device with high efficiency that is suitable for high frequency applications cannot be satisfied by semiconductor power devices with planar gates as produced by conventional technologies.
US publication No. 2007/0278571 discloses a cross-sectional view of a planar split-gate MOSFET device 130 as shown in FIG. 1C. The planar split-gate MOSFET device 130 is supported on a substrate 102 formed with an epitaxial (epi) layer 104. The MOSFET device 130 includes a split gate 132 with a gap g. The split gate 132 is disposed above a gate oxide layer 110 formed on top of the epitaxial layer 104. The MOSFET device further includes a shallow surface doped region 134 immediately below the gate oxide layer 110 to form a channel region. A vertical and deep JFET diffusion region 138 such as an N+ diffusion region is formed in the epitaxial layer 104 under the gap g of the split gate 132. This N+ region 138 counter-dopes the shallow surface doped layer and links the end of channel to the drain by extending from the top surface of epitaxial layer 104 to a bottom that is deeper than the bottom of a deep body region 136. The deep body regions 136 is doped with a dopant of second conductivity type, e.g., P-type dopant, extends from the bottom of shallow surface doped region 134 to a depth that is shallower than the bottom of deep JFET diffusion region 138. The P-body regions 136 encompassing a source region 108 doped with the dopant of first conductivity, e.g., N+ dopant. The source regions 108 counter-doping the shallow surface doped layer 134 are formed near the top surface of the epitaxial layer surrounding the JFET regions 138 formed underneath the gap of the split gates 132. The planar split-gate MOSFET structure shown in FIG. 1C has low gate-drain capacitance, since there is no gate electrode directly above the JFET diffusion 138. However these devices suffer from JFET pinching due to the current path running between body regions.
Lateral DMOS devices with grounded/substrate source of the prior art include P+ sinker or a trench used to connect the top source to the P+ substrate. “Comparative Study of Drift Region Designs in RF LDMOSFETs” to G. Cao et al., published in IEEE Electron Devices, August 2004, pp 1296-1303, discloses a cross-sectional view of a RF lateral DMOS device 150 device with grounded/substrate source as shown in FIG. 1D. The RF LDMOS device 150 is supported on a P+ substrate (source) 152 formed with a P− epitaxial layer 154 over it. The RF LDMOS device 150 includes P+ sinker 155 or a trench to connect top source metal 162 to the P+ substrate (source) 152. The top source metal 162 shorts the P+ sinker to the N+ top source region 159 through an opening in the oxide layer 160. A N+ drift region 156 is located at the top surface of the epitaxial layer 154 leading to the N+ drain region 158. A gate 166 is disposed above the N+ drift layer 156 and is electrically isolated by oxide 160. Top source metal 162 and drain metal 164 are disposed on top of the structure.
“A 2.45 GHz Power Ld-MOSFET with Reduced source inductance by V-Groove connections” to Ishiwaka O et al—published in International Electron Devices Meeting. Technical Digest, Washington D.C., USA, Dec. 1-4, 1985, pp. 166-169—discloses a LD-MOSFET with V-grooved source connections to minimize the source inductance (Ls), the gate-to-drain capacitance (Cgd) and the channel length (Leff). The V-grooves, which penetrates the P− type epitaxial layer and reach the P+ type substrate, are formed in the SiO2 region just outside the active area. The N+ type source regions of the LD-MOSFET are directly connected to the V-grooves with metallization. The source inductance Ls has become negligibly small because the device does not require the bonding wires for the source. The Cgd has also become a quarter that of the VD-MOSFET with the same gate width.
U.S. Pat. No. 6,372,557 discloses a method for forming a lateral DMOS transistor comprises: a) forming a first doped region of a first conductivity type in a semiconductor substrate of the first conductivity type; b) forming an epitaxial layer on the substrate; c) forming a second doped region of the first conductivity type in the epitaxial layer; and d) forming a body region of the first conductivity type in the epitaxial layer. The process of forming the first and second doped regions and the body region includes thermally diffusing dopants in these regions so that the first and second doped regions diffuse and meet one another. The body region also meets and contacts the second doped region. The body region is electrically coupled to the substrate via the first and second doped regions. Source and drain regions are then formed in the epitaxial layer. By forming the transistor in this manner, the electrical resistance between the body region and substrate can be reduced or minimized. Also, the size of the transistor can be reduced, compared to prior art lateral DMOS transistors. In essence, this type of device uses a buried layer to form part of the sinker region which connects the bottom source to the top of the device.
U.S. Pat. No. 5,821,144 discloses an insulated gate FET (IGFET) device (lateral DMOS transistor) with reduced cell dimensions which is especially suitable for RF and microwave applications, includes a semiconductor substrate having an epitaxial layer with a device formed in a surface of the epitaxial layer. A sinker contact is provided from the surface to the epitaxial layer to the substrate for use in grounding the source region to the grounded substrate. The sinker contact is placed at the periphery of the die in order to reduce the pitch of the cell structure.
U.S. Pat. No. 5,869,875 discloses a lateral diffused MOS transistor formed in a doped epitaxial semiconductor layer on a doped semiconductor substrate includes a source contact to the substrate which comprises a trench in the epitaxial layer filled with conductive material such as doped polysilicon, a refractory metal, or a refractory silicide. By providing a plug as part of the source contact, lateral diffusion of the source contact is reduced, thereby reducing overall pitch of the transistor cell.
However, the use of a sinker or trench increases the pitch of the cell due to the dimensions of the sinker or trench. In addition, most of the lateral DMOS devices of prior art use the same metal over source/body contact region and gate shield region and some of them use second metal for drain and/or gate interconnect, which are unreliable due to hot carrier injection.
US publication 20080023785 discloses a bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate integrated with a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. This device has a small cell pitch and achieves enhanced N-drift pinching on drain side to reduce hot carrier injection and gate-to-drain capacitance. However in this device and several of the previously described prior arts, the source is located at the bottom of the device, and is not suitable for certain applications which require the drain to be on the bottom.
US publication 20070013008 discloses a LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.
US publication 20070138548 discloses a LDMOS transistor device including a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.
However, the devices described in US Patent Publications 20070013008, and 20070138548 include an N+ drain contact region formed by deep vertical connections. N+ drain sidewall diffusion is shown to extend only in a P− region, but not in an N-LDD (N− lightly doped drain) region. This lateral extension of the N+ drain dopant will reduce the breakdown voltage (BV) by reducing the N-LDD lateral length. In addition, this device is susceptible to hot carrier injection because of lack of “drain engineering” to pinch off LDD region at drain edge of the gate.
U.S. Pat. No. 5,113,236 discloses a silicon on insulator (SOI) of integrated circuit comprising a plurality of components typically adopted for high voltage application having a semiconductor substrate of a first conductivity type, an insulating layer provided on the substrate, a semiconductor layer provided on the insulating layer, a number of laterally separated circuit elements forming parts of a number of subcircuits provided in the semiconductor layer, a diffusion layer of a second conductivity type opposite to that of the first conductivity type provided in the substrate and laterally separated from all the other circuit elements and means for holding the diffusion layer at a voltage at least equal to that of the highest potential of any of the subcircuits present in the integrated device. However, SOI technology is not preferred because it is expensive and results in a higher thermal resistance. The higher thermal resistance occurs because the heat dissipated in the active transistor, has to go out from the substrate, and the buried oxide in SOI films will have a higher thermal resistance than a standard bulk wafer. Furthermore, deep sinker diffusions are used, which reach from the top of the wafer to the substrate, and these will result in the need for large lateral spacing between the sinker and the active devices, especially as the epi layer (or device layer in the case of SOI based devices) becomes thick.
U.S. Pat. No. 5,338,965 discloses an integrated circuit RESURF (REduced SURface Field) LDMOS (Lateral Double-diffused MOS) power transistor combining SOI (Silicon-On-Insulator) MOS technology with RESURF LDMOS technology. A SOI transistor and a RESURF drain region are coupled together on the same substrate to provide a source isolated high voltage power transistor with low “on” resistance. This allows the RESURF LDMOS transistor to be advantageously used in applications requiring electrical isolation between the source and substrate.
This design is characterized by large lateral dimensions because the drift region is in the bulk substrate. In addition, the type of device shown in U.S. Pat. No. 5,338,965 is not a “bottom drain” structure as may be seen from a brief review of the figures therein.
It would be desirable to develop a LDMOSFET device, with SOI versions, that includes a low gate-to-drain capacitance and gate charge with the drain connection at the bottom for low-side power conversion applications and does not suffer from a current-pinching effect (JFET resistance) caused by the drain current having to flow vertically between two adjacent body regions.
It is within this context that embodiments of the present invention arise.